1. Field
Example embodiments present disclosure relates to a semiconductor device and a semiconductor system.
2. Description of the Related Art
A system-on-chip (SoC) may include at least one intellectual property (IP) block, a clock management unit (CMU), and a power management unit (PMU). The CMU provides a clock signal to at least one IP block, whereas the CMU stops the provision of the clock signal to the IP block that is not running, thereby reducing unnecessary resource waste in a system employing the SoC.
In order to control the provision of the clock signal, a clock gating technology is used. In order to implement clock gating, various clock sources, such as a multiplexing circuit (MUX circuit), a clock dividing circuit, a short stop circuit, and a clock gating circuit, included in the CMU, may be controlled by software using a special function register (SFR). However, generally, the control speed of the clock sources by software may be slower than the control speed of the clock sources by hardware, and the performance of the clock sources by software may be lower than the performance of the clock sources by hardware. Therefore, it is required to perform clock gating in a precise manner according to the operation environment of SoC by controlling various clock sources of the CMU in hardware.
Moreover, in order to reduce power consumption, a power gating technology may be used for various devices (for example, memory) that are electrically connected to the IP block and operable together. Similar to the clock gating technology, the power gating technology is also required to be processed by hardware.